The present invention generally relates to a spread spectrum communication system, and more particularly to a spread spectrum communication system having a minimized bit error rate so that a communication can be performed always in a preferable condition.
Generally, in a direct sequence spread spectrum communication system, a delay locked loop (DLL) is used as a tracking loop on a receiver side. The DLL assumes a delay in a pseudonoise (PN) signal, and generates a control signal having a variable polarization corresponding to a lead or a lag in an assumed value. The DLL corresponds to a phase locked loop (PLL) used for demodulating a frequency modulated (FM) signal. A typical DLL is known as a baseband DLL, a non-coherent DLL or a dithering loop. Normally, when these DLLs are used as a tracking loop, a loop gain of the DLL is, in most cases, fixed to a predetermined value.
Various design methods have been discussed for a communication system using the PLL as a tracking loop. Most of those discussions are related to how to eliminate a steady-state phase error or a tracking error. However, in a case where a demodulated signal is related to the steady-state phase error as is in a clock rate modulation spread spectrum (CRM-SS) communication system, it is not appropriate to design a communication system by using a design method in which the steady-state phase error is aimed to be merely reduced.
As a known document describing prior art related to the present invention, there is a publication titled "Method of using PLL-IC" (published by Sangyo Shuppan, pages 112-124, Chapter VII, Feb., 10, 1986). This publication describes optimum designs of the PLL in accordance with their objects for use. However, this publication does not describe a design in which the DLL is used or a design in which a phase error defined by a sum of the steady-state error and the tracking error is used.
FIG. 1A is a block diagram of an example of a transmitter of a conventional CRM-SS communication system; FIG. 1B is a block diagram of an example of a receiver of the conventional CRM-SS system.
In the transmitter shown in FIG. 1A, a clock signal generated by a voltage controlled oscillator 1 is frequency modulated by an information signal supplied thereto, and then a PN signal is generated in a pseudonoise generator (PNG) 2 in accordance with the modulated clock signal supplied by the voltage controlled oscillator 1. The PN signal is output to a radio-frequency (RF) unit 3 so as to be transmitted by means of a carrier wave via an antenna 4.
In the receiver shown in FIG. 1B, the carrier wave (PN signal) is received by a front end unit 6 via an antenna 5. The front end unit 6 demodulates the carrier wave to obtain the PN signal. The PN signal is split by a correlation network 7. A reference PN signal generator 11 generates two reference PN signals, one having a lead and the other having a lag. The reference PN signals are input to the correlation network 7. In the correlation network 7, each of the reference PN signals is multiplied by the split PN signal, and the difference between the two products is output as an error signal to an amplifier 8. The error signal is amplified by the amplifier 8 and smoothed by a loop filter 9, and then supplied to a voltage controlled oscillator 10 to generate a clock signal to be supplied to the reference PN signal generator 11. A demodulated signal is obtained as an output of the loop filter 9.
In the above-mentioned conventional CRM-SS communication system using the DLL on a receiver side, there is a problem in that an attempt to reduce a bit error for a conventional PLL system cannot be applied because the DLL inherently uses a phase difference, and thus the bit error cannot be reduced by merely reducing the phase error in a simple manner.